Filter banks, part 2: Optimization and synthesis

High Level Synthesis Architectural Optimization Basics
In part 1 of this article we introduced basic filter bank theory and used the Synplify DSP High Level Synthesis (HLS) tool to implement an example filter bank into three alternative architectures. In part 2 we dive deeper into these three architectures to better understand how these filters work. We will also examine the HLS optimizations we applied and the resulting benefits.

Example Filter Bank Review
Before we proceed, let's quickly review our filter bank example. Our example, shown in Figure 1, is a size 16 DFT filter bank. The color scheme shows the sample rate change where a 16 MHz input sample rate (red) has been chosen and the output sample rate is downsampled by 16 (green).

(Click to enlarge)
Figure 1. Length 16 DFT filter bank model using vector and multi-rate elements in Synplify DSP and Simulink.

As discussed in part 1, the Synplify DSP tool synthesizes high-level models into RTL. As part of this synthesis, Synplify DSP tool can perform a wide variety of optimizations. These optimizations fall into two broad categories:

1. Automatic optimizations at the IP, Operator, and RTL level

2. User-specified system-wide architectural optimizations: Retiming, Folding and Multi-Channelization

All optimization decisions depend on the target FPGA and ASIC—in this case, we are targeting a Xilinx Virtex-5 FPGA—as well as the timing specified in the model. For our DFT filter bank example we have a 16 MHz input sample rate and an output rate of 1 MHz. Therefore, all optimizations made must meet this timing. Given these constraints, the Synplify DSP HLS engine attempts to minimize area.

Figure 2 illustrates the area reductions possible by applying optimizations. The baseline result automatically applies basic FIR architecture optimizations on coefficient symmetry and trivial coefficients to reduce hardware multiplier usage. The results for user-specified optimization reflect folding factors of x1 and x4.

Figure 2. LUT-equivalent area of architecture optimizations for length 16 DFT filter bank example. Polyphase transformation and folding synthesizes architectures with significantly lower area.

It is worth noting that all optimizations maintain behavioral accuracy. This allows Synplify DSP to generate an RTL simulation test bench that matches the model simulation.

Page 2: Baseline Optimization
Page 1 | 2 | 3 Related Links: How to use M and Simulink for DSP hardware design Multirate DSP, part 1: Upsampling and downsampling Unite algorithm and hardware design flows

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