Using DFM Routing to Impact Design Performance and Yield

INTRODUCTION
There are have been numerous papers written on the techniques that can be employed during integrated circuit (IC) design to achieve better overall manufacturability and yield. These design-for-manufacturing (DFM) techniques have historically been grouped by the yield limiting affects that they are meant to mitigate, such as wire spreading for particulate (or random) based yield loss, influence rules for systematic (or lithography) based yield loss and metal density control for parametric yield.

While these DFM techniques were useful, they lacked a strategy for easy deployment and acceptance by the design community. Many times, the designers were expected to understand complex relationships between different yield limiters and even if they did understand, the industry was slow to provide sufficient fab data to allow the designers to make the necessary trade-offs. When data became available the bigger problem became that there was no automation in place to help designers implement the trade-offs. Because of this much of what has been espoused as DFM had been relegated to the design of smaller IP blocks where designers could manually handle the required trade-offs.

In an effort to realize a more wide spread use of DFM techniques, Microsoft, Pyxis, PDF and Ponte conducted an experiment to establish a methodology for proactively using DFM techniques during the routing phase of the design flow and create a strategy for quantifying the performance and yield impacts of that methodology.

EXPERIMENT OVERVIEW

Experimental Test Block
The design used in the experiment is an established production device for which both performance and yield are known. To simplify the experiment one block of the design was used that represented approximately ten percent of the chip area as shown in Figure 1. The chosen block is actually replicated four times throughout the chip and is made up of both standard cells and custom memories. The block area was approximately 85% utilized by the standard cells and memories and thus represented a fairly constrained environment in which to practice DFM techniques.

1. Test block seen in the chip floorplan.

Basic block statistics were as follows:

• Number of cell instances: ~ 1.4 million
• Number of signal nets: 1.1 million

Strategy for Results Comparison
Since the design was already in production it was used to compare results against the experimental layout. A copy of the original block was made using the existing standard cell and memory placements along with the corresponding power and clocking structures and timing constraints. The rest of the routing was stripped out of the block and the block was re-routed and optimized using a correct-for-manufacturing approach with the Pyxis NexusRoute manufacturing-aware router.

Yield comparisons were done using yield analysis tools from Ponte Solutions, Inc. and PDF Solutions, Inc. The layout from both the taped-out block and the experimental block were run through these tools to understand the difference in the predicted yields given the original block and DFM style layouts. Ponte's Yield Analyzer (YA) tool was used to simulate yield loss due to particulates (random) and via failures (single vs. double via coverage). PDF Solutions Yield Ramp Simulator (YRS) was used to simulate yield loss due to systematic via misalignment and via density failures.

Timing for the experimental block was compared to the timing of the taped-out design. Parasitics for the both blocks were calculated using the Pyxis parasitic extractor. Delay calculation and static timing analysis were performed using Synopsys' PrimeTime and PrimeTime-SI products along with the parasitics generated by the Pyxis extraction tool. Timing slack histograms of both the taped-out design and the experimental block were compared. All timing comparisons were done inclusive of all DFM treatments.

Design & Data Flow
Data was exchanged between the existing design flow and the Pyxis NexusRoute product by using standard interface formats as shown in Figure 2. LEF was used to pass technology data and rules; DEF was used to pass standard cell and memory IP block placements, power rails, blockages etc. Design connectivity and timing constraints were passed using Verilog, DEF and Synopsys Design Constraints (SDCs). PrimeTime and PrimeTime-SI were used for delay calculation and static timing analysis. Parasitics generated by the Pyxis extractor were passed to PrimeTime and PrimeTime-SI through the SPEF format.

2. Design and Data Flow used in the experiment.

Methodology for DFM Implementation
A methodology for proactively using DFM techniques during the routing phase of the design flow was put in place using the Pyxis NexusRoute product. Some of the basic assumptions and tenets of the methodology were as follows:

• The routing phase should fit seamlessly into the design flow and behave like a normal design flow using standard interface formats to exchange data
• The routing phase should use the same floorplan and timing constraints as the original block flow
• DFM techniques should be introduced as early into the routing phase as possible to enable the greatest degrees of freedom for optimizing the design both in terms of performance and yield
• Use of a correct-by-construction approach whereby DFM is built into the design from the beginning as opposed to finding and fixing problems post-routing which could then affect timing
• Use of recommended design rules when ever possible but do so in an automated fashion so that the designer does not have to decide when or when not to use these rules
• Route the design in an automated fashion using DFM techniques during routing to help close timing
• Use a progressive timing closure approach to use the minimize the number of constraints put on the router to address timing and signal integrity closure

DFM Routing Methodology
Routing was done in three stages as shown in Figure 2. The methodology employed works to accomplish the items detailed in each stage as follows.

A. Global Route Stage

1. Overall route planning with 3D wire balancing for metal density and density gradient control
2. 2D wire spreading to reduce critical areas for shorting defects
3. Automated progressive timing closure flow using wire and netlist optimization. Includes wire layer assignment and use of non-default rules for DFM and for signal integrity / cross talk avoidance.
4. 2D extraction with estimations for congestion and eventual metal fill
5. PrimeTime and PrimeTime-SI are used for delay calculation and STA

B. Detailed Route Stage

1. Signals are routed correct-by-construction layout with incremental DRC during routing
2. 2D wire spreading for DFM
3. All routing is cost-based; allocates space for DFM
1. Preferred design rules
2. Replacement of single vias with double vias
3. Other via treatments if vias can not be doubled
4. Widening of wires to reduce critical area for "open" type defects
5. Protection of lithography sensitive patterns
4. DFM treatments are committed where the space reserved is available after detailed routing.
5. DFM analysis is done internal to the Pyxis tool using pDfx^TMmodels from PDF Solutions

C. Metal / Via Fill Stage

1. Metal fill is added to bring density up to required goals. Metal fill is kept at least 3X minimum spacing away from signal wires and can be tied or left floating.
2. A via density check is made and vias are added to reach a required density.
3. 2.5D extraction is performed on the final layout including the metal and via fill. Delay calculation and static timing analysis is again performed using PrimeTime-SI.

In general as much optimization as possible was done during the global route stage. These optimizations were then passed on to the detailed route stage as constraints.

Pyxis' progressive timing closure flow was used to automatically make several passes through the global router. Incremental 2D extraction, delay calculation and timing analysis using PrimeTime were performed upon iterations. Additional routing constraints were automatically generated on each pass until both timing and DFM goals were met. During the global route stage the router did a sensitivity analysis of the design's timing paths and selectively used non-default routing rules for signal integrity and cross talk avoidance. Final timing optimizations were done using netlist gate sizing techniques.

Upon meeting timing and DFM goals at the global route stage, the design was sent through the detailed route stage. During the detailed route stage, wires were routed using a dynamic costing algorithm that reserved space for the various DFM treatments as detailed in the above described method. As part of the methodology, the router used a combination of preferred design rules and costing to reserve as much space for DFM treatments as possible. After routing, DFM treatments such as double vias, wide wires etc. were committed to the layout based upon the amount of reserved space left un-used. As before PrimeTime-SI was used to perform delay calculation and static timing analysis. After completing the detailed route stage the design was sent through the metal / via fill stage. Density goals were set for metal and via density as well as density gradients for metal using a 10um X 10um window stepped in 5um increments. A final 2.5D extraction, delay calculation and static timing analysis were done to ensure metal and via fill did not negatively affect timing.

After all routing stages were complete the experimental layout block was analyzed for errors using Mentor Graphics' Calibre' DRC and LVS tools.

During each stage of the routing process, progress towards DFM goals were checked using analysis capabilities included in the Pyxis NexusRoute software. The NexusRoute installation included fab fail rate process models from PDF Solutions which were used to analyze and Pareto the areas of highest possible yield impact for the design. Parameters of the NexusRoute software were adjusted to achieve optimum yield given feedback from these analysis. Final GDS data was analyzed for yield loss using Ponte Solutions' Yield Analyzer and PDF Solutions' Yield Ramp Simulators. Results from both blocks are compared below.

Yield Limiters Targeted for Optimization

Random Yield	Systematic Yield
Critical area for opens	Via protection(for litho and misalignment)
Critical area for shorts	litho-based wire protection
Single vs. double vias	Via density
	Metal density and density gradient

Page 2: EXPERIMENT RESULTS
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