FPGAs have long been used as primary and co-processors in telecommunications. Digital signal processing (DSP) in industrial applications often has fundamental differences from the typical telecommunication application. In telecommunications, the input data is commonly high data rates with real time processing constraints requiring completion of calculations between successive input data buffers or samples. With a DSP processor, this may allow for only a few tens of instructions per input data sample. This instruction bandwidth limitation can be minimized by taking advantage of the multiple processing units in some DSP processors. However, creating the specialized pipe-lined code to take true advantage of this parallelism requires hand optimization of assembly language routines. Maintenance, re-usability, and implementation of this type of code can be troublesome and expensive at best. Additionally, the degree of parallelism (simultaneous executions) is relatively low, and may still not permit the real time processing constraints to be met.
A better alternative for high-bandwidth computations is to use an FPGA as a co-processor that integrates the repetitive, speed-critical portions of an algorithm into the FPGA. With an FPGA and automated design software, design engineers have the ability to optimize system performance in ways not possible with a traditional DSP. This article discusses the general issues of moving part, or all, of a DSP industrial application onto an FPGA using system software design tools.
Automated Software Design Suite
The design software referred to in this article consists of three main components: Quartus II, SOPC Builder, and DSP Builder development tools. Collectively, these tools comprise an automated system development platform that provides a high level of design integration and flexibility, allowing engineers to focus on their target design at the system level rather than at the level of HDL and logic construction.
These are is the logic-level design tools that support embedded processor software development, DSP datapath design, synthesis, place-and-route, verification, and device programming. They perform the lower-level functions of producing a programmed FPGA from the set of design files passed to the development tools. These tools can be used separately or in conjunction, and are able to produce the equivalent as an HDL (Verilog or VHDL) design methodology, at a fraction of the effort. System designers do not need to be a VHDL or Verilog programmers. The automated system generation tools allow the components of a hardware system are defined, inter-connected, simulated, and verified, all without resorting to the underlying HDL. With a true point-and-click design method, system architects can generate entire systems, simulate and verify it, and download it into an FPGA all from the PC desktop.
